The invention is related to the field of integrated circuits.
The duty cycle of a clock signal is the ratio of the xe2x80x9conxe2x80x9d time to the total time period of the clock cycle. Integrated circuits, such as microprocessors, rely on clock generators to provide a clock signal. The clock generator can include a phase locked loop (PLL) device and an oscillator. The PLL receives an external frequency signal from the oscillator and locks onto the external frequency. The PLL can then send the frequency to divider circuits to divide the frequency of the signal to a desired duty cycle, such as 50% for example. The duty cycle can then be distributed throughout the integrated circuit. However, the duty cycle may travel through a number of buffers, which may distort the duty cycle.
For example, clock distribution circuits typically use inverters or buffers to drive the clock signal. While a PLL controls the frequency and typically also the duty cycle, the duty cycle may become distorted due to variations between the P and N devices of the distribution inverters. If buffers are used, this distortion will be reduced as the signal passes through two stages, but clock skew will be increased by the additional delay. Furthermore, to moderate the duty cycle, the PLL must generate a clock two times the frequency of that required by the circuit.
One approach that has been implemented to address these problems is shown in FIGS. 1A and 1B, which show a current-starved inverter in schematic and functional form. In this approach, devices 110 and 120 are connected in series to serve as controlled current sources 130 and 140 for inverter 150, which includes devices 112 and 122. By controlling the current sources 130 and 140, the output slew of output clock signal 160 can be adjusted to maintain the duty cycle of input clock signal 105. However, as processes scale and Vcc decreases, the headroom used by the series devices 110 and 120 significantly decreases the range of control allowed by this approach. Additionally, there is some non-linearity at the ends of the control range in this circuit.